Rule #2: When creating a latch model, use a non-blocking assignment statement.
Rule #3: Blocking assignment statements are used when building a combined logical model in the always block.
Rule #4: A non-blocking assignment statement is used when there is a combination and timing logic in an always block.
Rule #5: Do not use both blocking and non-blocking assignment statements in an always block.
Rule #6: Do not assign values ​​to multiple same blocks in the same variable.
Rule #7: Call the $strobe system function to display the value assigned with a non-blocking assignment statement.
Rule #8: Do not use #0 delay assignment.
1. Description completeness of sensitive variables
In Verilog, when using the always block to design a combinational logic circuit, all signals participating in the assignment at the right end of the assignment expression must be listed in always @ (sensitive level list), and the expression of the if statement in always must be at a sensitive level. Listed in the list. If a signal not listed in the sensitive level list is referenced at the right end of the assignment expression, a transparent latch will be implicitly generated for the unlisted signal during synthesis. This is because the change of the signal does not immediately cause the change of the assigned value, but must wait until one of the signals in the sensitive level list changes, its function is expressed, that is, there is a transparent latch, which is The change of the signal is temporarily stored, and when a certain signal in the sensitive level list changes, the pure combination logic circuit cannot do this. The synthesizer will issue a warning.
Example1:
Input a,b,c;
Reg e,d;
Always @(a or b or c)
Begin
e=d&a&b; /*d is not in the list of sensitive levels, e does not change immediately when d changes, until a change in a, b, c */
d=e |c;
End
Example2:
Input a,b,c;
Reg e,d;
Always @(a or b or c or d)
Begin
e=d&a&b; /*d In the list of sensitive levels, e changes immediately when d changes*/
d=e |c;
End
2, the description of the completeness of the condition If the conditional description of the if statement and the case statement is incomplete, it will also cause unnecessary latches.
Example1:
If (a==1'b1) q=1'b1;//If a==1'b0,q=? q will keep the original value and generate a latch!
Example2:
If (a==1'b1) q=1'b1;
Else q=1'b0; / / q has a clear value. No latches will be generated!
Example3:
Reg[1:0] a,q;
....
Case (a)
2'b00 : q=2'b00;
2'b01 : q=2'b11; / / If a == 2'b10 or a == 2'b11, q = ? q will keep the original value unchanged, the latch!
Endcase
Example4:
Reg[1:0] a,q;
....
Case (a)
2'b00 : q=2'b00;
2'b01 : q=2'b11;
Default: q=2'b00; //q has an explicit value. No latches will be generated!
Endcase
1, the bit width of the port is best defined in the I / O description, not in the data type definition;
Example1:
Module test(addr,read,write,datain,dataout)
Input[7:0] datain;
Input[15:0] addr;
Input read, write;
Output[7:0] dataout; //To define the bit width of the port like this!
Wire addr,read,write,datain;
Reg dataout;
Example2:
Module test(addr,read,write,datain,dataout)
Input datain, addr, read, write;
Output dataout;
Wire[15:0] addr;
Wire[7:0] datain;
Wire read,write;
Reg[7:0] dataout; // Do not define the bit width of the port like this! !
2. The relationship between port I/O and data type:
The data type of the port's I/O port
Module internal module external
Input wire wire or reg
Output wire or reg wire
Inout wire wire
3, the left end of the assign statement must be wire; directly with "=" to assign a value to the variable, the left end of the variable must be reg!
Example:
Assign a=b; //a must be defined as wire! !
********
Begin
a=b; //a must be defined as reg!
End
For example, A is an INTEGER type with a range from 0 to 255; B is an STD_LOGIC_VECTOR, defined as 8 bits. When A is added to 255, it will remain unchanged at 255 and will not be automatically inverted to 0 unless it is 0. When B is added to 255, adding 1 will automatically reverse to 0. So pay special attention when using it!
Take the trigger as an example to illustrate the normative description
1, no set / clear timing logic
Always @( posedge CLK)
Begin
Q<=D;
End
2. The timing logic with asynchronous set/clear is asynchronously set/cleared. It is independent of the clock. When the asynchronous set/clear signal arrives, the output of the flip-flop is immediately set to 1 or 0. The clock edge is asserted/cleared. Therefore, the set/clear signal must be included in the event control expression of the always block.
Always @( posedge CLK or negedge RESET)
Begin
If (!RESET)
Q=0;
Else
Q<=D;
End
3. Timing logic with synchronous set/clear. Synchronous set/clear means that the output of the flip-flop can be converted to 1 or 0, respectively, only when the valid transition time of the clock is set/cleared. Therefore, do not include the set/clear signal in the event control expression of the always block. However, the level of the set/clear signal must first be checked in the always block.
Always @( posedge CLK )
Begin
If (!RESET)
Q=0;
Else
Q<=D;
End
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