How to use your own IP core in EDK?

How to use your own IP core in EDK? This is what many people dream of. However, in the various documents of EDK and ISE, this is obscured.

In previous designs, whether it was a simple IPIF, or to add some modifications to the IP core that is open in the EDK. It used to be very distressing!
There have been unexpected gains recently.
Whether you join an EDK IP core or a core generate will find a data folder such as: C:\Xilinx\12.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\xps_central_dma_v2_01_c\data
There will be an important file in this folder. Xps_central_dma_v2_1_0.mpd, xps_central_dma_v2_1_0.pao.
The role of these two files is to define the external port, and secondly to compile the file, the order of compilation. But what do you need to embed a FIFO when you modify it, DSP? We know that these nuclei are often in the form of ngc or edn. This is due to a bdd file. For example, plbv46_pcie_v2_1_0.bbd. Its contents are as follows:
############################################################################ ####################################################
##
## Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
##
## opb_pci.bbd
##
## Black Box DefiniTIon
##
############################################################################ ####################################################

Files
afifo_16x136.ngc, dpram_36_512.ngc, dpram_36_512_32.ngc, dpram_36_1024.ngc, dpram_136_512.ngc, dpram_70_512.ngc, fifo_37x512.ngc, fifo_37x512_32.ngc, fifo_136x16.ngc, fifo_136x512.ngc, fifo_70x16.ngc, fifo_70x512.ngc, fifo_72x512. Ngc, fifo_70x32.ngc, fifo_71x512.ngc
This shows that so many "cores" are used in PCIE. Second, one thing to note is the devl folder. This folder is often generated when an IP core is generated. Inside this file is an ISE project. In fact, ISE has already prepared for you, but it has not been clearly told you. Use this project correctly. You will be pleasantly surprised.

Other household electric appliance

tcl , https://www.tclgroupss.com