Network routers are equipped with statistical counters to monitor performance, manage traffic, track network activity, and enhance security. These counters keep track of the number of packets entering and exiting the network, as well as specific events like packet errors. Each time a packet arrives or leaves, multiple counters are updated. However, the number of available counters and their update rate is often constrained by memory technology.
Managing these counters requires high-performance memory capable of handling frequent read-modify-write operations. This article introduces a unique statistical counter that utilizes the IP method. One end of the counter connects to a Network Processing Unit (NPU), while the other connects to a Xilinx QDR-IV memory controller. The QDR-IV Statistics Counter IP is a soft IP built on QDR-IV SRAM, offering efficient statistical counting for network communication and other counter-based applications.
**QDR-IV SRAM Overview**
The QDR-IV SRAM features two bidirectional data ports, A and B, which can perform two writes, two reads, or one read/write operation per clock cycle. This flexibility allows architects to optimize performance in scenarios where read and write operations are not balanced. Each port supports DDR (Double Data Rate) operation, enabling data transmission on both rising and falling edges of the clock. The burst mode allows two words per cycle, with each word being either 18-bit or 36-bit wide. The address bus is general-purpose, providing separate addresses for Port A and Port B on each edge. Some manufacturers also offer embedded ECC (Error Checking and Correction), significantly reducing soft errors and improving reliability.
There are two types of QDR-IV SRAM: High Performance (HP) and Ultra High Performance (XP). HP devices operate at up to 667 MHz, while XP devices reach 1066 MHz. The XP version improves performance by dividing memory into eight banks, controlled by the three least significant bits of the address. This allows access to different memory modules in the same cycle, maximizing RTR (Read-Then-Write) performance. System designers can plan the architecture to fully utilize this capability, enhancing performance while lowering overall costs.
**Statistics Counter IP**
The QDR IV Statistical Counter is a soft IP based on QDR-IV SRAM, designed for network communication management and other counter applications. It uses read-modify-write logic to support system management access. One end connects to the NPU, and the other to the QDR-IV storage controller. Since it supports line cards at 400 Gbps and higher, its performance is limited only by the FPGA and QDR-IV devices used.
**Statistics Counter IP Operation**
Figure 1 illustrates a use case involving QDR-IV and the statistical counter IP. A typical NPU sends a statistical (STATS) update request at 800 million per second. Each request includes an entry/exit packet command token with two counters (packet and byte counts) in a 72-bit word. The entire counter cache is updated to a lifetime counter (usually DRAM) every second. This process, known as a processor (PROCS) update request, is transmitted via PCIe to update the lifetime counter. The figure shows the setup of the STATS IP, QDR-IV memory, Xilinx memory controller, PCIe bus, and NPU.
**Statistical IP Architecture**
As shown in Figure 2, the STATS_IP architecture consists of three main components: the Same Address Comparison Pipeline (SACOMP) block, the Request-Multiplex-Demultiplex (REQ_MXDMX_CHn) block for each channel, and the QDR IV application channel per channel. The SACOMP block has two pipeline stages: one for comparing all four channels on the same clock cycle, and another for comparing the same address across a single channel. If multiple channels have the same address, the highest-priority channel accumulates the data, preventing inconsistencies.
The REQ_MXDMXChn block handles processor and statistical requests, ensuring no overlapping updates. After processing each one-second update, it stops the processor request for a set number of clocks to avoid consecutive updates. The ABCH_CTRLn block implements the read-modify-write mechanism, ensuring data consistency and accurate updates.
**QDR-IV Interface Operation and Application Channel Mapping**
The statistical stream operates over four channels, with a one-second update from the processor. The QDR-IV controller uses 4:1/1:4 channel multiplexing/demultiplexing with a dedicated four-channel port interface. In HP mode, requests are processed in the order Ch0-Ch1-Ch2-Ch3, while in XP mode, they follow an odd-even pattern to prevent conflicts. This ensures optimal performance and data integrity across different configurations.
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