Network routers rely on statistical counters for performance monitoring, traffic management, network tracking, and security purposes. These counters track the number of packets entering and exiting the network, as well as specific events like packet errors. Each packet arrival triggers updates to multiple counters, but the number and update rate of these counters are often constrained by storage technologies.
To manage these counters efficiently, high-performance memory is required to handle frequent read-modify-write operations. This article introduces a unique statistical counter design that leverages the IP method. One end of the counter connects to a network processing unit (NPU), while the other connects to a Xilinx QDR-IV memory controller. The QDR-IV Statistics Counter IP is a soft IP solution that integrates with QDR-IV SRAM, offering efficient statistical counter capabilities for network communication and other applications.
**QDR-IV SRAM Overview**
The QDR-IV SRAM features two bidirectional data ports, A and B, capable of performing two writes, two reads, or one read/write operation in a single clock cycle. This flexibility allows architects to optimize applications where read and write operations may not be balanced. Both ports support DDR (Double Data Rate) operation, transmitting data on both clock edges. The burst mode allows for two words per clock cycle, either 18-bit or 36-bit wide. Address buses are general-purpose, with rising and falling edges providing addresses for Port A and Port B, respectively. Some manufacturers also offer embedded ECC (Error Checking and Correction), which significantly reduces soft errors and enhances reliability.
There are two types of QDR-IV SRAM: High Performance (HP) and Ultra High Performance (XP). HP devices operate at up to 667 MHz, while XP devices reach 1066 MHz. The XP version improves performance by dividing memory into eight banks, controlled by the three least significant address bits. This allows access to different memory modules within the same clock cycle, enabling full utilization of RTR (Read-Then-Write) performance. System designers can plan their architecture to maximize efficiency, leading to better performance and lower costs.
**Statistics Counter IP**
The QDR IV Statistical Counter is a soft IP solution that uses QDR-IV SRAM for network communication and other counter applications. It supports system management access via read-modify-write logic. One side connects to the NPU, and the other connects to the QDR-IV storage controller. Since it supports line cards at 400 Gbps and above, its performance depends only on the FPGA and QDR-IV devices used.
**Statistics Counter IP Operation**
Figure 1 illustrates how the QDR-IV SRAM and statistical counter IP work together. A typical NPU sends a STATS update request at 800 million per second. Each request includes an entry/exit packet command token with two counters (packet and byte counts) in a 72-bit word. The entire counter cache is updated to a lifetime counter (usually DRAM) every second. This readback from the NPU is known as a PROCS update request. PCIe is used to transmit the counter cache data.
The figure shows the configuration of the STATS IP, QDR-IV memory, Xilinx memory controller, PCIe bus, and NPU.
**Figure 1:** Complete infrastructure with statistical IP, NPU, and memory
The statistical IP works with both HP and XP QDR-IV memories. Its operation is controlled by a single parameter at the top-level interface. Each counter stream (packets and bytes) uses a 72-bit word. A 144 Mb QDR-IV SRAM can support four million counters. The number of IP interfaces corresponds to the number of QDR-IV SRAMs used.
As shown in the block diagram, the NPU sends statistics and processing requests over a 4x25 Gbps link. The IP operates at a quarter of the memory access frequency and uses four parallel data paths, called "channels," to match memory bandwidth. In HP and XP modes, Port A acts as a read port, and Port B as a write port. Each statistical request performs a read-modify-write operation on a unique storage location.
Read and write requests are delayed to match the QDR-IV memory's read latency and memory controller latency. This phased design also handles service update requests during local cache latency. In HP mode, there is no restriction on address assignment across channels. However, in XP mode, channels 0 and 1 are assigned to odd addresses (ingress data), and channels 2 and 3 to even addresses (egress data), preventing block-limited locations.
A one-second processor readback request is common in both modes. The entire memory must be read back every second, so the processor issues requests at one-second intervals, resetting each memory location upon a read request.
**Statistical IP Architecture**
Figure 2 shows the architecture of the STATS_IP module, consisting of three subcomponents: the Same Address Comparison Pipeline (SACOMP) block, the Request-Multiplex-Demultiplex (REQ_MXDMX_CHn) block for each channel, and the AB Channel Pair Counter Logic (ABCH_CTRL_CHn) block.
**Figure 2:** Statistical IP Architecture
The SACOMP block has two pipeline stages: one for comparing all four channels on the same clock cycle (SACOMP_ChN-to-All), and another for comparing the same address on a single channel (SACOMP_B2BChN). If multiple channels have the same address, the highest-priority channel accumulates the data, invalidating others to prevent inconsistencies. This ensures that a single statistical request covers all relevant channels.
The REQ_MXDMX block receives processor and statistical update requests. Since the processor update interval is fixed, it selects the next clock-cycle request and stops statistical requests using a backpressure signal. After processing each one-second update, it disables the processor channel for a set number of clocks to avoid consecutive updates. This prevents new requests until the backpressure signal clears.
In the final phase, the ABCH_CTRL block implements the actual read-modify-write mechanism for each statistical request, ensuring processor requests stay current. It includes read-delay pipelines, control multiplexing, read-write pipelines, and QDR-IV controller interface logic. Feedback mechanisms and control multiplexing eliminate data consistency issues.
**QDR-IV Interface Operation and Application Channel Mapping**
The statistical stream uses four channels and one second (processor) update to define application channels. The QDR-IV controller uses 4:1/1:4 channel multiplexing/demultiplexing with dedicated four-channel port interfaces for QDR-IV Ports A and B. The controller processes channels in a fixed order (ch0, ch1, ch2, ch3) at 4X clock frequency. Figure 3 shows the QDR-IV controller sequence and recommended application channel mapping for HP and XP statistical counter solutions.
**Figure 3:** QDR-IV interface 4:1/1:4 multiplexing/demultiplexing and application channel mapping
In the QDR-IV HP statistical counter, requests for Ports A and B are independent and follow the order ch0-ch1-ch2-ch3. In contrast, the QDR-IV XP statistical counter arranges requests in an odd-even pattern to avoid conflicts between Ports A and B in the same clock cycle.
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