Design of flow scheduling model A-Flow

Design of flow scheduling model A-Flow

1.1 The traditional data packet scheduling strategy and its improvement in the active network In the active network, each node will process data packets with programs. The processing of input data packets is not conducive to resource management due to the following two reasons: 1) When a data packet is received, the time required to process the interruption cannot be imposed on any application, because the destination address of the data packet is unknown and needs to be checked The content of the data packet is determined; 2) The memory required to receive the data packet cannot be immediately calculated and allocated.
The traditional solution to this type of problem is to simplify the handling of invalid data packets as much as possible. To this end, the processing of data packets is divided into two steps: packet classification and subsequent protocol processing. Packet classification mainly determines the recipient of the data packet, and its idea is mainly reflected in the protocol layering: a layer of the protocol stack uses a field in the header of this layer to determine which protocol the data packet is sent to the upper layer. Subsequent protocol processing focuses on the resource control of the recipient. The delay processing technology of the network packet LRP is to solve the problem of too much time spent on the processing of those packets that eventually need to be discarded, resulting in a serious drop in network throughput (especially In the case of network overload) [2].
LRP is implemented in C language in the kernel space, and is limited to the processing of traditional IP packets. In order to schedule active packets and traditional IP packets at the same time, and from the perspective of security of mobile code, this paper proposes an A-Flow model based on traditional network technology and implemented in user mode using Java language, which is allocated for each active data flow. In a flow queue, the active packets related to the upper layer EE will be directly delivered to the upper layer for calculation processing, and the other active packets will be handed over to the default flow processing, which can greatly reduce the processing time of invalid data packets.

1.2 The main module design of A-Flow As shown in Figure 1 in the A-Flow model, the Flow Manager uses the method of registering the data flow, which can shield the impact of the underlying network transmission technology on the upper active computing function; flow processing The Flow Processor implements core functions such as packet caching, authentication, and payload scheduling. Other auxiliary classes include Flow Buffer for packet buffering, Flow Dispatcher to declare the prototype of the dispatch function, and Flow Dispatcher (ANEPDispatcher) to transfer the data packets to the correct flow. The following are the implementation of the main modules:

Figure 1 Flow scheduling model A-Flow

1) Flow scheduling interface First, you need to define the Dispatcher interface to schedule input packets. The interface declares an abstract function dispatchBuffer (). A Dispatcher either caches a packet, or points to another Dispatcher that caches the packet.

2) Stream scheduler A class ANEPDispatcher that implements the Dispatcher interface can complete the identification and distribution of the input data stream. The algorithm is relatively simple:
First check the active network identifier (ANid) in the Buffer.
If the ANid is already registered in the Flow Dispatcher of an EE, the Buffer is sent to the Flow.
If an ANid is not registered and the Discard bit is not set (whose value is identified by the Flags field in the ANEP packet header), then this Buffer is scheduled to the default Flow.
Otherwise, the Buffer is discarded.

3) Flow processor This is the core class of the A-Flow model. It has three functions: (1) Data packet caching. There are two queues in each stream: one is the free queue (freeBuffers), the other is the used queue (usedBuffers). The latter is used to store data packets that have been received but not yet delivered. Unless an idle queue is available, the data packets cannot be cached. The user must ensure that there is sufficient cache available. (2) Payload scheduling. A Processor is associated with another Dispatcher. Therefore, the payload of all data packets distributed to a processor should also be distributed to the Dispatcher associated with it, so as to achieve protocol layering. Before scheduling, the Processor will add its own header length to the scheduling offset. (3) Data packet authentication. The processor must be able to identify whether a packet belongs to a flow. This can be done by analyzing the data it carries. The processor completes the scheduling of the input stream through the following process. First, the Processor checks whether its freeBuffers queue is empty. If it is empty, it means that the Flow Buffer space has been used up, that is, the processor is not given enough memory. In this case, simply discard the packet without additional processing. If it is not empty, the Buffer is removed from the queue and "exchanged" with the system Buffer in the scheduling path. In this way, the Buffer containing the data is inserted into the processor's receive queue.

4) Flow Manager This class provides a set of methods to register Flow Processor in the system. It provides a method to directly access the device, or to access the existing protocol stack, such as IPv4 / UDP protocol. The following is an example of registering a UDP stream:
IniTIalizaTIon:
private Hashtable udpFlows = new Hashtable ();
Register Flow module: registerUDPFlow (int port, FlowDispatcher fd)
Integer udpPort = new Integer (port);
UDPFlow udpFlow = (UDPFlow) udpFlows.get (udpPort);
if (udpFlow == NULL) then
udpFlow = new UDPFlow (port, fd);
udpFlows.put (udpPort, udpFlow);

5) Copying packets in the stream buffer queue is one of the operations that Dispatcher cannot complete. Because a data packet may be transmitted to multiple Flow Processors for processing, it requires its own writable data backup. The first processor that receives a packet exchanges its freeBuffers with the system buffer that received the packet. This buffer contains the actual data, called the original buffer (originalBuffer). The rest of the Processor will also perform the same operation, but the obtained Buffer does not contain the actual data, which is called the dependent Buffer (dependentBuffer). The originalBuffer and dependentBuffer are connected by a linked list.
When writing or matching on a Buffer, you must first declare it as "independent", which means: remove it from the linked list, and copy the data if necessary. There are two cases: 1) For dependentBuffer, you need to copy the original data to its memory before deleting the Buffer from the linked list; 2) For originalBuffer, you need to copy the data to the first dependentBuffer first, and It is declared as the originalBuffer of the remaining Buffer. The purpose of setting the Buffer as a related list is to avoid a large amount of actual data copying when a Buffer needs to be sent to multiple destinations.

Research on Active Network Flow Scheduling Model A-Flow

APM Ac Power Source model SP300VAC1500W provides a complete AC test solution with built in arbitrary waveform generator to simulate many types of power waveforms, at power levels up to 1500 VA.With better accuracy and faster response time, The dc and Ac Output Power Supply offers greater advantage for R&D and compliance tests.The application is from bench-top testing to mass production.

This AC source model SP300VAC1000W adopts high speed DSP+CPLD control, high frequency PWM power technology and active PFC design to realize AC/DC stable output.

Some features as below:


  • 4.3"large touch color screen
  • AC+DC mixed or independent output mode
  • Capable of setting output slope/phase angle  
  • Built-in IEC standard test function
  • Built-in multiple protections
  • Built-in power meter
  • Support impedance function
  • Support for LIST/PULSE/STEP mode & Transient mode
  • Standard RS232/RS485/USB, Optional GPIB//LAN
  • Support harmonics/inter-harmonics simulation and measuring function
  • Support for USB data import/export and scree nap from front panel 


1500W AC Power Supply

1500W Ac Power Supply,Adjustable 1500W Power Supply,1500W Power Supply,Ac Dc Power Source

APM Technologies (Dongguan) Co., Ltd , https://www.apmpowersupply.com