**1 Introduction**
WiMAX, short for Worldwide Interoperability for Microwave Access, is a global standard for microwave access that enables high-speed wireless communication. It is also known as the IEEE 802.16 standard or Broadband Wireless Access (BWA). WiMAX is a wireless metropolitan area network technology designed to operate in microwave and millimeter wave frequency bands. One of the key components used in BWA applications is the SMI7035 dual-band single-chip transceiver from Sierra Monolithics. This chip is specifically designed for low-cost customer premise equipment (CPE) and supports a wide range of WiMAX-based products. Its advanced features make it an ideal choice for wireless broadband solutions.
**2 Key Performance Characteristics [1]**
- Operating frequency range: 3.3–3.8 GHz or 2.3–2.7 GHz.
- High receive sensitivity of -100 dBm with a gain control range of at least 75 dB.
- Transmitter gain control range of up to 55 dB.
- Dual-band operation with support for both fractional and integer frequency synthesizers.
- Integrated two frequency synthesizers for improved flexibility and performance.
- Fractional frequency synthesizer: 125 kHz channel spacing, conversion time less than 90 μs.
- Integer frequency synthesizer: 2 MHz channel spacing, conversion time less than 90 μs.
- SPI interface for configuration and control by a microprocessor.
- Power supply: +5V and +3.3V.
- Low power consumption of 1.73 W.
- Built-in Received Signal Strength Indication (RSSI) for signal monitoring.
- Compact 48-pin QFN package with dimensions of 7 × 7 mm.
**3 Internal Architecture**
The SMI7035 is composed of several critical blocks including the receiver, transmitter, signal strength indicator, and frequency synthesizer. These components work together to ensure efficient and reliable wireless communication over a wide range of frequencies.
**3.1 Receiver Section**
The receiver employs a quadrature down-conversion architecture. The incoming RF signal is first amplified by a low-noise amplifier, filtered, and then mixed with a local oscillator signal from the fractional frequency synthesizer. This process generates a high intermediate frequency (IF) signal, which is further processed through an external surface acoustic wave (SAW) filter to isolate the desired frequency. The signal is then down-converted again using the integer frequency synthesizer, resulting in a low IF signal that is amplified, filtered, and delivered via differential output pins RX_IF_P and RX_IF_N.
**3.2 Transmitter Section**
The transmitter section receives baseband data through the TX_IF_P and TX_IF_N pins. After amplification, the signal is mixed with a local oscillator from the integer frequency synthesizer and filtered. The resulting IF signal is then further converted using the fractional frequency synthesizer, producing the final RF signal. This signal is amplified and transmitted at either 2.3–2.7 GHz or 3.3–3.8 GHz through the TX_RF pin.
**3.3 Received Signal Strength Indication Circuit (RSSI)**
The RSSI circuit processes the intermediate frequency signal to generate a DC voltage proportional to the received signal strength. This information can be used for various purposes such as fault detection, handshaking, and selecting the appropriate RF channel.
**3.4 Frequency Synthesizer**
The frequency synthesizer includes both integer and fractional frequency division components, allowing for precise and flexible frequency generation.
**3.4.1 Integer Frequency Division Synthesizer (Based on Charge Pump PLL)**
The integer frequency synthesizer uses a phase-locked loop (PLL) with a charge pump to control the voltage-controlled oscillator (VCO). When the input signal is applied, the phase detector compares the input and VCO outputs, generating an error signal that adjusts the VCO frequency until the loop is locked. This results in an output frequency that is an integer multiple of the reference frequency. However, this approach limits the frequency resolution to the reference frequency itself.
**3.4.2 ∑-△ Modulation Fractional Frequency Division PLL**
The fractional frequency synthesizer uses ∑-△ modulation to achieve sub-integer frequency division, allowing for finer frequency resolution. In this design, the frequency division ratio consists of an integer part (N) and a fractional part (F), enabling non-integer multiples of the reference frequency. This method improves system bandwidth, reduces adjustment time, and enhances phase noise performance. The fractional division is achieved by alternating between dividing by N and N+1 over multiple reference cycles, controlled by a phase accumulator overflow mechanism.
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