China's First Domestic Design SoC Will Be Produced by the End of This Year

Cao Ansheng, vice president of business development at Shenzhen Microelectronics Technology Co., Ltd. (ICUBE), recently told the media: “China’s first high-efficiency general-purpose processor IC1 adopting Harmony Unified Processor Technology will be sampling in early July and is expected to be released at the end of this year. Into the mass production phase, this SoC hits the top three in China: China's first dual-core processor with its own instruction set architecture, and China's first SoC that truly integrates CPUs and GPUs on a single die, China The first multicore processor chip based on parallel computing and with advanced synchronous multithreading design."

IC1 has two MVP cores and is manufactured on 65nm process. The maximum clock frequency is 600MHz. The maximum operating power consumption is less than 1W. It supports OpenGL ES2.0 and OpenGL, supports all decoding formats of HD 720p, supports 5.1-channel audio, and processing capability. Reached 5160DMIPS, peak performance equivalent to 4.8GHz single-core serial processor.

Cao Ansheng pointed out: "IC1's GPU performance is quite advanced. It can generate up to 70 million triangles per second and 600 million pixels per second. This performance is very close to the nVidia GPU. On the other hand, IC1's die size is only 27. Square millimeters, while the Tegra 2 for nVidia requires 50 square millimeters, and the Apple A5 processor requires 122 square millimeters."

IC1 is based on the core MVP (Multithreaded Virtual Pipeline) core developed by ICUBE. The MVP has the following eight characteristics: first, a processor core based on parallel computing that has been integrated with the instruction set architecture; and secondly, a maximum clock frequency of 600MHz, 65nm. Process, four threads; third, superscalar instruction execution pipeline provides stable high performance: 3.6 GFLOPS or 2580 DMIPS; fourth, up to 8 dynamic thread cores, with hardware load balancing, and software configurable at the same time Thread technology; Fifth, support data parallelism, task parallelism, and functional parallel computation modes, and reduce interrupt demand and content switching; sixth, core memory includes 64KB instruction cache, 64KB data cache, 64KB SRAM, 8-channel DMA, and 16 interrupts. Source controller; seventh, the kernel area including memory is only 3mm2, and the power consumption is as low as 300mw. Eighth, through native compilation and MVP driver, simultaneous and heterogeneous parallel computing API interfaces are supported simultaneously. .

The Significance of Harmony and Harmony to the Industry Harmonization Unified processor technology marks a milestone for the global semiconductor industry because it innovatively integrates two different types of processors on a single die: central processing unit CPU and graphics processor GPU. This technology consists of a multi-threaded virtual pipelined parallel computing core, an independent instruction set architecture, an optimized compiler, and a fast-switching dynamic load balancer. It is expected that it will bring the most cost-effective and energy-efficient processing performance to the Android-based tablet mobile computing and mobile communications market by the end of this year.

The processors on the market today are based on designs from decades ago, which limits their use of the latest semiconductor technologies. The Harmonized Unified Processor technology sets a new industry standard for processor performance with its ability to handle up to four threads (tasks) on each core. This is a huge breakthrough compared with the processing technology in the market where one core can only handle one thread. This additional parallelism will bring huge performance improvements to mobile computing, which brings a long-awaited solution to tablet manufacturers because it can greatly enhance the user experience.

ICube CTO Simon Moy concluded: “Developing your own IP from scratch is a key differentiating point between ICube and other Chinese technology companies. This gives us a bigger space for innovation, compared to other chip companies. We are able to take advantage of the latest semiconductor technologies and reduce the cost of our SoC products. We are proud to have attracted and established a world-class development team, including Silicon Valley system architects who have participated in PowerPC development and local talents in China.”

Cao Ansheng stated that we can now provide ICEM's development platform QEMV to customers and we plan to introduce a 4-core general-purpose processor next year in Q3.