Broadly speaking, FPGA configuration includes programming the FPGA device directly using the download cable, programming the external EEPROM and FLASH, programming the FPGA device using the MPU, and programming the device with external EEPROM and FLASH.
There are three main types of FPGA device configuration: active configuration, passive configuration, and JTAG configuration.
Active configuration: The configuration operation is guided by the FPGA device.
Passive configuration: The configuration process is controlled by a computer or controller. After power-up, the control device or master sends the data stored in the external memory to the FPGA device, and the device I/O and registers are initialized after configuration is complete. After the initialization is complete, enter user mode and start normal operation.
Once the designer has chosen the FPGA system configuration, the MSEL pin on the device needs to be set to a fixed value to indicate the current configuration.
Commonly used configuration methods are:
Passive Serial ConfiguraTIon: Passive Serial Configuration
AS configuration (AcTIve Serial ConfiguraTIon): Active serial configuration
Passive Parallel Synchronous ConfiguraTIon: Passive Parallel Synchronization Configuration
Fast Passive Parallel Configuration: Fast Passive Parallel Configuration
Passive Parallel Asynchronous Configuration: Passive Parallel Asynchronous Configuration
Passive Serial Asynchronous Configuration: Passive Serial Asynchronous Configuration
JTAG configuration (Joint Test Action Group Configuration)
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