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Abstract: gm5020 is a highly integrated image processing chip produced by Canadian genesis for liquid crystal displays and other dot matrix displays. The features, functions and principles of the chip are introduced. The plasma color TV was designed with gm5020, and its hardware structure and software flow were given.Keywords: plasma color TV on-screen display gm5020
Plasma color power safe to avoid radiation, is 100% green TV. Due to the influence of magnetic gas and magnetic field, it has the advantages of slim body, light weight, large screen, bright colors, clear picture, high brightness, small distortion and space saving. Plasma color TV (PDP) realizes the three-in-one of TV, computer and telecommunications, which directly meets the requirements of broadband multimedia information network. PDP TV is one of the current directions for large-scale color TVs. In the future digital era, it will gradually replace the huge box-shaped CPT display and become the leading product in the future color TV market. The world's largest PDP manufacturers have announced the launch of new PDP products, indicating that the PDP has begun to leap into the big stage of the display market. However, the high price of PDP has severely restricted its popularity.
The gm5020 is designed to be a flat panel display with simple, flexible and low cost. Most liquid crystal displays at home and abroad use this chip. We use the gm5020 to design plasma color TVs to reduce the cost of plasma TVs.
1 gm5020 features and functions
The gm5020 is a highly integrated image processing chip produced by Genesis Canada for liquid crystal displays (LCDs) and other dot matrix displays. It has the following main features:
(1) three ADC inputs (RGB) as input to a computer graphics card;
(2) an 8-bit ITU-R BT656 video input signal (YUV) port;
(3) A digital video interactive interface (DVI) containing high-bandwidth digital information encryption protection (HDCP);
(4) has image enlargement/reduction/freeze function;
(5) A function with on-screen display (OSD) control;
(6) There is a single-chip microcomputer with an 8051 structure on the chip;
(7) A function with frame rate conversion (FRC) control;
(8) The video working frequency is up to 160MHz;
(9) The highest resolution SXGA is 1280×1024;
(10) providing an output interface supporting a flat panel display (LCD or PDP) and an output interface supporting the CRT display;
(11) providing a 9-wire bidirectional data interface (GPIO) connected to the external MCU;
(12) A 2-wire I2C interface and a 6-wire I2C interface;
(13) It has the function of adjusting the chromaticity, contrast, brightness, and saturation of RGB and YUV signals.
The gm5020 has a supply voltage of 3.3V and is available in 292pin and 27mm x 27mm PBGA packages. The block diagram of gm5020 is shown in Figure 1.
With the exception of four external clocks, all clocks are internally generated by the gm5020 through direct digital synchronization (DDS) to generate the required synchronous clock.
The gm5020 has two reset modes: hardware reset and software reset. The hardware reset refers to resetting the gm5020 after the reset pin (T1) of the gm5020 is connected to the low level for 1 μs . Software reset refers to resetting gm5020 by setting bit SOFTWARE_RESET=0 in register HOST_CONTROL.
The gm5020 can accept three input data modes: (1) 24bit RGB; (2) 8bit ITU-RBT656 (CCIR626 422); (3) digital video interactive signal DVI.
The gm5020 is capable of measuring the line scan (HS) and field scan (VS) time parameters of the input video signal for detecting whether the input video signal has changed and determining the mode of the input video signal.
The gm5020 is capable of background, brightness, chrominance, contrast, and saturation adjustment of captured digital image data.
There are mutually independent horizontal and vertical zooming and zooming functions, the values ​​of which are determined by the input image size and the enlarged image size.
Frame rate conversion (FRC) of video input data and video output data is implemented through a frame storage interface.
The gm5020 provides two OSD modes: character mode and graphics mode. The character mode supports simultaneous display of 4 color fonts, and the graphics mode supports 256 color displays. The OSD can store word tables or bitmaps in internal SRAM or externally extended SDRAM. By setting the OSD register, you can control functions such as font size, size, display position color, flicker, background transparency, background opacity, and rotation.
The Gm5020 provides an output interface that supports a flat panel display (LCD or PDP) and an output interface that supports a CRT display. The output interface signals include 18-bit and 24-bit RGB pixel data, display enable (DEN), display clock, line sync (DHS), and field. Signals such as synchronization (DVS), all displayed data and clock are synchronized with the output time DCLK, and its display can be programmed through the I2C interface.
2 gm5020 register description
The gm5020 has a total of 512 internal control registers, which can be programmed via the I2C interface to control the gm5020 for various functions. The following is a description of some of the registers.
General configuration register: 00h is used to record the company ID, version number and chip serial number respectively; 0x006H, 0x0d5h, 0x0d6h are used for FRC setting.
Input mode control register (0x50h, 0x004h, 0x6dh, 0x74h): Used to set the input signal mode ADC.
ADC register (50h~6Ah): Used to set the parameters of RGB (red, green, blue).
TMDS Register (6Bh~73h): Used to set the parameters of DVI.
YUV register (7dh~86h): Used to set the parameters of YUV when the input signal Video is decoded to YUV.
Input mode register (8dh~A4h): parameters for storing the input signal mode, including the horizontal display start position of the input signal, the horizontal display end position, the vertical display start position, the vertical display end position, the horizontal display delay, and the vertical level. Display delay.
Measurement Registers (A9h to b6h): Store HS, VS, and HT that measure RGB and TMDS signals into this register.
Input Clock Register (1Bh ~ 20h): Includes six read and write registers for setting the appropriate clock pulse.
Output register (156h~1DFh, 1FFh): used to define the horizontal scan bus number HT, vertical scan bus number VT, horizontal display start position, horizontal display end position, vertical display start position, vertical display end position of the output display And frame delay, etc.
OSD Control Registers (11Ah to 153h): These registers allow you to define the four colors used in the OSD mode and OSD and the respective parameters of the two OSD windows.
Background Brightness Control Register (24h~29h): PWM is set by these registers to adjust the background brightness of the LCD.
GPIO Control Register (24h~29h): Used to detect the input status and output indication status of the keyboard.
Application of 3 gm5020 in PDP display system
2 is a hardware circuit structure diagram of the gm5020 applied to a PDP flat panel display system.
The MCU uses a programmable chip AT89C51RD2 with a 64K Flash ram, and the software code is stored in the chip. The role of the MCU is: (1) receiving commands from the keyboard or remote control. (2) Set the video decoder, gm5020, TV tuner, and PT2313 registers through the I2C bus to complete the specified functions.
The video decoder uses Samsung LG's KS0127, Video, S-Video, component-Video signals are input to KS0127, and KS0127 converts the video analog signal into YUV data that satisfies the BT656 protocol and transmits it to gm5020.
The TV tuner uses Philips' Fl1236MK2 to select channels via the I2C bus. The RF signal is decomposed by the TV tuner to generate Video and Audio signals.
The volume controller uses a four-channel PT2313 to select channels through the I2C bus, controlling volume, balance, Treble & Bass, and Loudness.
SDRAM uses LG's K4S16162, SDRAM capacity of 16M, mainly used to store image data.
The serial port chip adopts ICL232CPE for CMOS/TTL level conversion, and is used for communication between MCU and PC. Realize software modification of plasma color TV.
The YUV signal from the video decoder, the RGB graphics signal of the PC, and the digital video interactive signal (DVI) are processed by the Gm5020 chip to directly drive the plasma display.
4 system software design
The program flow chart of the software in the PDP flat panel display system is shown in Figure 3. The system software is mainly divided into three parts:
(1) Initialization: mainly includes MCU initialization, global variable initialization, gm5020 internal MCU initialization, video decoding initialization.
(2) Input signal mode detection: Automatically recognize Video, NTSC/SECAM, and support display of Video, S-Video, Componen-Video. Detects no signal input status and prompts, and is in standby state after 1 minute.
(3) User parameter setting: 1 display size. 2 Image reduction/enlargement, with 16:9, 4:3 screen switching. 3 image brightness, contrast, saturation adjustment. 4 output image line frequency HS, field frequency VS, field scan bus number VT. 5 Image position adjustment: The image position is moved left and right, up and down, and the image position is left and right and upside down. 6 images are frozen.
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